The European Processor Initiative held a codesign workshop on September 10 and 11, in Heraklion, Greece.
This two-day workshop brought together leading researchers and industry experts to explore the future of high-performance computing in Europe. Key topics included performance analysis with EPAC, next-generation chip architectures (Arm, RISC-V), chiplet technologies, and reliability challenges. The program featured keynotes on energy-efficient computing and exascale systems, alongside project experiences from projects closely collaborating with EPI (including EUPEX, EUPILOT, and DARE). Prof. Kovač, who is also the Chief Communication Officer for EPI, as well as group representative in all these other projects for HPC FER, held a presentation related to FAUST© FPU, designed by HPC FER Center researchers.
FAUST© is a high-performance, pipelined, customizable floating-point unit (FPU) designed for integration into RISC-V cores with vector processing capabilities. It is designed with a focus on minimizing its silicon area while maintaining a rich feature set and full compliance with the IEEE 754-2019 and RISC-V Vector extension (RVV) v1.0 standards with numerous customization capabilities to address various customer needs.
Director Kovač presented all the capabilities and specifications of the developed FPU and invited the attendees to get in touch with HPC FER group for licensing.
The presentation is available in our repository.
